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MTC20154
INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
Features

Fully integrated AFE for ADSL Overall 12 bit resolution, 1.1MHz signal bandwidth 8.8 MS/s ADC 8.8 MS/s DAC THD: -60 dB @ full scale 1V full scale input Differential analog I/O Accurate continuous-time channel filtering 3rd & 4th order tunable continuous time LP Filters 64 pin TQFP package 350mW power consumption
TQFP64 (10 x 10 1.4mm) ORDERING NUMBER: MTC10154TQ-C (Temp.: 0 to 70C)
intended to be used with the MTC20156/ MTC20147 DMT/ATM processors as part of the MTK20150/MTK20141 chipsets, but may also be used to support other xDSL signal processors. The MTC20154 provides programmable low pass filters for each of the two channels and automatic gain control. A configuration pin allows the filters to be switched from ATU-R mode to ATU-C mode. The pipeline ADC architecture provides 13 bit dynamic range and a signal bandwith of 1.1 MHz. The device consumes only 0.35 Watt in full operation and has a power down mode for standby. It is housed in a compact 64 pin thin plastic quad flat package.
Applications
ADSL Front-end for all full rate and Lite standards
DESCRIPTION The MTC20154 is the fifth generation Analog Front End (AFE) designed for DMT based ADSL (Asynchronous Digital Subscriber Line) modems compliant with ANSI T1.413 category 2 standard. It includes one 12 bit DAC and one 13 bit ADC.It is Figure 1. Block Diagram
T uning circuit I/V - Ref Xtal-driver VCXO DAC
ICCQ Calibration
CTRL/TST ifce
Error Correction
G= -9..6dB 1dB step TXP TXN AGCtx 1.1MHz HC/DS A = -15..0dB, 5dB step G = -0..31dB, 1dB step RXP RXN 138KHz SC/US
ADC
MUX 13bits 4bits
DAC 12bits
MUX 4bits
AACrx AGCrx
February 2004
Digital interface
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MTC20154
Functional Description The MTC20154 chip can be used on the ATU-C side (LT), and on the ATU-R (NT) side (defined by LTNT pin). The selection consists mainly of a filter interchange between the RX and TX path. The filters (with a programmable cutoff frequency) use automatic continuous time tuning to avoid time varying phase characteristics which can be of dramatic consequence for DMT modems. It requires few external components, uses a 3.3 V supply and is packaged in a 64 pins TQFP in order to reduce PCB area. The Receiver (RX) The DMT signal coming from the line to the MTC20154 is first filtered by the two following external filters: - POTS HP filter: Attenuation of speech and POTS signalling. - Channel filter: Attenuation of echo signal to improve RX dynamic. The signal is amplified by a low noise gain stage (-15..+31 dB) then low-pass filtered to avoid anti-aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise. A 12 bits A/D converter samples the data at 8.832 MS/s, transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface. The Transmitter (TX/TXE) The 12 bits data at 8.832 Ms coming from the DMT signal processor through the digital interface are transformed by a D/A converter into an analog signal. This signal is then filtered to decrease DMT sidelobes levels and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal for the external line driver and in case of short loops provide attenuation provision (-9..+6 dB). The VCXO The VCXO is divided in a XTAL driver and an auxilliary 8 bits DAC for timing recovery. The XTAL driver is able to operate at 35.328 MHz or 17.664 MHz. An internal PLL will be used to double the frequency in the 17.664 MHz case. It also provides an amplitude regulation mechanism to avoid temperature/-supply/technology dependent frequency pulling. The DAC which is driven by the CTRLIN pin provides a current output with 8 bits resolution and can be used to tune the XTAL frequency with the help of external components. A time constant between DAC input and VCXO output can be introduced (via the CTRLIN interface) and programmed with the help of an external capacitor (on VCOCAP pin). The Digital Interface The digital part of the MTC20154 can be divided into two parts: The data interface converts the multiplexed data from/to the DMT signal processor into a valid representation for the TX DAC and RX ADC. The control interface allows the board processor to configure the MTC20154 paths (RX/TX gains, filter band, ...) or settings. Package The MTC20154 is housed in a 64-pin TQFP package.
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MTC20154
Pin Assignement Table 1. Pinning Description MTC20154 AFE
Pin Name Description Connection Type Dir. Main characteristics
Digital interface 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DVSS TX3 TX2 TX1 TX0 CTRLIN DVDD DVDD CLKM CLKWD RX3 RX2 RX1 RX0 PD DVSS RESET Negative supply for input I/Os + core Transmit data bus bit 3 (MSB) Transmit data bus bit 2 Transmit data bus bit 1 Transmit data bus bit 0 (LSB) Serial control interface input Positive supply for input I/Os + core Positive supply for output I/Os Master clock output Word clock output Receive data bus bit 3 (MSB) Receive data bus bit 2 Receive data bus bit 1 Receive data bus bit 0 (LSB) General power down Negative supply for output I/Os General reset (active low) Dig supply MTC20156/146/147 MTC20156/146/147 MTC20156/146/147 MTC20156/146/147 MTC20156/146/147 Dig supply Dig supply System System MTC20156/146/147 MTC20156/146/147 MTC20156/146/147 MTC20156/146/147 System Dig supply System Direct Bi Z=0 high Z high Z high Z high Z high Z Z=0 Z=0 Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Z=0 High Z
Schmitt In Schmitt In Schmitt In Schmitt In Schmitt In Direct Direct Bi Bi
Tristate Out Tristate Out Tristate Out Tristate Out Tristate Out Tristate Out Tristate Out Direct Bi
Schmitt In
Analog interface 17 18 19 20 22 AVSSADC DRVSD DRV1 DRV0 VREF ADC analog negative supply External TX driver shutdown External TX driver bias control MSB External TX driver bias control LSB ADC virtual ground decoupling Ana supply TX driver TX driver TX driver C network Direct Bi Z=0 Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF NoDC current
Tristate Out Tristate Out Tristate Out Analog Bi
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Table 1. Pinning Description MTC20154 AFE (continued)
Pin 23 24 25 29 30 31 32 33 34 35 36 39 40 43 44 48 50 51 52 53 54 55 56 57 58 Name VRAN VRAP AVDDADC AVDD TXDRV TXN TXP AVSS TXDRV GP3 GP2 GP1 GP0 AVDDFILT AGND AVSSFILT AVSSLNA AVDDLNA RXN RXP XTAL bypass PLL DACVREF AVDDDAC Description ADC negative reference decoupling ADC positive reference decoupling ADC analog positive supply Internal TX pre--driver positive supply Analog TX signal negative output (diff) Connection C network C network Ana supply Ana supply TX output Type Analog Analog Direct Direct Analog Analog Direct Dir. Bi Bi Bi Bi Out Out Bi Main characteristics NoDC current NoDC current Z=0 Z=0 V com = VDD/2 V com = VDD/2 Z=0 Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Imax = 4 mA Cmax = 100 pF Z=0 NoDC current Z=0 Z=0 Z=0 V com forced at VDD/2 V com forced at VDD/2 High Z High Z NoDC current Z=0 Z=0 X cap sensitive X cap sensitive
Analog TX signal positive output (diff) TX output Internal pre--driver negative supply Analog general purpose control pin Analog general purpose control pin Analog general purpose control pin Analog general purpose control pin Filter analog positive supply Analog virtual ground Filter analog negative supply LNA analog negative supply LNA analog positive supply Ana supply Board Board Board Board Ana supply C network Ana supply Ana supply Ana supply
Tristate Out Tristate Out Tristate Out Tristate Out Direct Analog Direct Direct Direct Analog Analog Bi Bi Bi Bi Bi In In
Analog RX signal negative input (diff) RX input Analog RX signal positive input (diff) Crystal oscillator bypass selection pin PLL enable/disable selection pin DAC voltage reference decoupling DAC analog positive supply RX input Strap Strap C network Ana supply Ana supply Crystal Crystal
Schmitt In Schmitt In Analog Direct Direct Analog Analog Bi Bi Bi Bi Bi
AVDD XTAL Crystal driver analog positive supply XTALO XTALI Crystal driver connection 1 Crystal driver connection 2
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Table 1. Pinning Description MTC20154 AFE (continued)
Pin 59 60 61 62 63 Name AVSS XTAL AVSSDAC IVCO VCOcap VCXOI Description Connection Type Direct Direct Analog Analog Analog Dir. Bi Bi Bi Bi Bi Main characteristics Z=0 Z=0 DC current No Dc current DC current
Crystal driver analog negative supply Ana supply DAC analog negative supply VCO steering current reference VCO external capacity connection VCO steering current output Ana supply VCO Capacity VCO
Mode selection interface 26 27 LTNT TEST Mode selection: LT or NT (static) Test mode selection (static) Strap Strap Schmitt In Schmitt In high Z high Z
Analog test access interface 41 42 46 47 T2N T2P T1P T1N Neg. diff input/output test access Pos. diff. input/output test access Pos. diff output test access Neg. diff output test access Test Test Test Test Analog Analog Analog Analog Bi Bi Out Out V com = VDD/2 V com = VDD/2 V com = VDD/2 V com = VDD/2
Figure 2. MTC20154 Grounding and Decoupling Networks
Analog VDD 10F
AVDD each pin must have its own capacitor 100nF
10F 100nF
VRAP pin 25 100nF 10F 100nF VREF pin
10F 100nF
VRAN pin 26
OAC VREF DAC 10F 100nF
AVDD AVOD 100nF VCOcap pin
38 AGND pin
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Figure 3. Pin connection (Top view)
XT ALbypass AVDDXTAL AVSSXTAL DACVREF AVSSDAC AVDDAC VCOcap VCXOI XT ALO
DVSS
XT ALI
IVCO
RXN 50
RXP 51
64
63
62
61
60
59
58
57
56
55
54
53
52
TX3 TX2 TX1 TX0 CTRLIN DVDD DVDD CLKM CLKWD RX3 RX2 RX1 RX0 PWD DVSS RESETN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
N.C.
PLL
48 47 46 45 44 43
AVDDLNA T1N T1P N.C. AVSSLNA AVSSFILT T2P T2N AGND AVDDFILT N.C. N.C. GP0 GP1 GP2 GP3
MTC20154-TQ ADSL Analog Front End
42 41 40 39 38 37 36 35 34 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30 TXN
31 TXP
ELECTRICAL RATINGS AND CHARACTERISTICS Absolute Maximum Ratings Operation of the device beyond these limits may cause permanent damage. It is not implied that more than one of these conditions can be applied simultaneously. Table 2. Electrical Characteristics
Symbol VDD Vin Tstg TL Pd Tj Parameter Any VDD supply voltage, related to substrate Voltage at any input pin Storage Temperature Lead Temperature (10 second soldering) Power Dissipation Junction Temperature 350 -40 350 Min. -0,5 -0,5 -40 Typ. Max. 5 VDD +0.5 125 300 500 110 Unit Vhh V C C mW C
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AVDDTXDRV
AVSSTXDRV
AVSSADC
DRVSD
VREF
VRAP
DRV1
DRV0
AVDDADC
VRAN
L TNT
TEST
N.C.
N.C.
32
MTC20154
Operating Conditions Unless specified, the characteristic limits of 'Static characteristics' in this document apply for the following operating conditions: Table 3. Operating conditions
Symbol AVDD DVDD Vin, Vout Tamb Tamb Parameter AVDD supply voltages, related to substrate DVDD supply voltages, related to substrate Voltage at any input and output pin Ambient Temperature - I version Ambient Temperature - C version Min. 3.0 2.7 0 -40 0 Max. 3.6 3.6 VDD 85 70 Unit V V V C C
Static Characteristics Digital Inputs Schmitt-trigger inputs: TXi, CTRLIN, PDOWN, LTNT, RESETN, TEST Table 4. Digital Inputs
Symbol VIL VIH VH Cinp Low level input voltage High level input voltage Hysteresis Input capacitance 0.8*DVDD 1.0 1.3 3 Parameter Min. Max. 0.2*DVDD Unit V V V pF
Digital Outputs Hard driven outputs: RXi, CLKWD, GPI, DRVI, DRVSD Table 5. Digital Outputs
Symbol VOL VOH Cload Parameter Low level output voltage High level output voltage Load capacitance Test Condition Iout = -4 mA Iout = 4mA .85*DVDD 30 Min. Max. .15*DVDD Unit V V pF
Clock Driver output: CLKM Table 6. Clock Driver output
Symbol VOL VOH Cload Dcycle Parameter Low level output voltage High level output voltage Load capacitance Duty cycle 45 Test Condition Iout = -4 mA Iout = 4mA .85*DVDD 30 55 Min. Max. .15*DVDD Unit V V pF %
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Analog TX/RX Signals The reference impedance for all power calculations is 100. DMT Signal A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125 KHz with a total number of 256 carriers (ANSI). For large N, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, the signal is clipped to trade-off the resulting SNR loss against AD/DA dynamic range. A clipping factor (Vpeak/Vrms = "crest factor") of 5 is used resulting in a maximum SNR of 75 dB. ADSL DMT signals are nominally sent at -40 dBm/Hz +/- 3 dB (-3.65 dBm/carrier) with a maximal power of 100 mW for downlink transmitter and 4.5 mW for uplink transmitter. The minimum SNR+D needed for DMT carrier demodulation is about (3*N+20) dB with a minimum of 38 dB where N is the constellation size of a carrier (in bits). Table 7. Signal Levels (on the line)
LT side Description Max level Max RMS level Min level Min RMS level RX 839 mVpdif 168 Vrms 54 mVpdif 11 mVrms TX 15.8 Vpdif 3.16 Vrms 3.95 Vpdif 791 mVrms RX 3.95 Vpdif 791 mVrms 42 mVpdif 8 mVrms 3.4 Vpdif 671 mVrms 839 mVpdif 168 mVrms NT side TX
Table 8. Total Signal Level (on the line)
LT side Description Max level for receiver RX 4 Vpdif (Long line) NT side RX 4.2 Vpdif (Short line)
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ATU-C Side Block Diagram The transformer at the ATU-C side has a 1:2 ratio. The termination resistors are 12.5 in case of 100 lines. The hybrid bridge resistors should be < 2.5 k for low-noise. An HP filter must be used on the TX path to reduce DMT sidelobes and out-of-band noise influence on the receiver. On the RX path, a LP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech and signalling. Figure 4. ATU-C AFE Schematics (For detailed schematics see MTB-20150-EBC reference design.)
POTS
LINE Zo=100
LP Pots Filter 35.328 MHz or 17.664 MHz
VCXOI 2:1
Pots Filter RXT1
R
RXT2
R
Master clock 35.328 MHz
VCODAC RXP [0:1] -15.. 31db LNA
VCXO
Nibbles 17.664 MHz Word 8.832/4.416 MHz 13bits 8.832 MS/s 4.416 MS/s
12.5
12.5
4 CTRLIN LTNT=1 RESETN
LP 138 KHz
RXN [0:1]
MTC-20154
Gtx line driver H P F
-g..+6db TXP 4 P.D. TXN LP 1.1 MHz D/A convertor
12bits 8.832 MS/s 4.416 MS/s
Interface to MTC-20146/147/156
L P F
D/A convertor
2R
2R
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ATU-R Side Block Diagram The ATU-R side block diagram is equal to the ATU-C side block diagram with the following differences: - The transformer ratio is 1:1 - Termination resistors are 50 for 100 lines. An LP filter may be used on the TX path to reduce DMT sidelobes and out-of-band noise influence on the receiver. On the RX path, a HP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech and signalling. Figure 5. ATU-R AFE Schematics (For detailed schematics see MTB-20141-EBR reference design.)
POTS
LINE Zo=100
LP Pots Filter VCXOI 2:1 Pots Filter
VCXO
35.328 MHz or 17.664 MHz
RXT1 R
RXT2 R
Master clock 35.328 MHz
VCODAC RXP [0:1] L P F RXN [0:1] 0.. 31db LNA
VCXO
Nibbles 17.664 MHz Word 8.832/4.416 MHz 13bits 8.832 MS/s 4.416 MS/s
50
50
4 CTRLIN LTNT= 0 RESETN
LP 1.1 MHz
MTC-20154
Gtx line driver H P F
-g..+6db TXP 4 P.D. TXN LP 138 KHz D/A convertor
12bits 8.832 MS/s 4.416 MS/s
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Interface to MTC-20146/147/156
D/A convertor
2R
2R
MTC20154
MTC20154 RX PATH Speech Filter An external bidirectional LP filter for up and downstream POTS service splits out the speech signal to the analog telephone circuit on both the NT and LT sides of the line. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but guarantees that the POTS bandwidth is not disturbed by spurious signals from the ADSL spectrum. Channel Filters The purpose of these external analog circuits is to provide partial echo cancellation by analog filtering of the receive signal for both ATU-R (reception of downstream channel) and ATU-C (reception of upstream channel). This is feasible because the upstream and the downstream data can be modulated on separate carriers (FDM). Signal Attenuator (ATT) and Low Noise Amplifier The attenuator needs to be DC decoupled from the external circuitry. In fact, it is also used to internally fix the LNA input common mode voltage at the nominal value: AVDD/2. This is done by the use of an internal biasing circuit. It is therefore mandatory to decouple the MTC20154 input from any external DC biasing system. The Low Noise Amplifier (LNA) placed after the ATT will be used in combination with the attenuation block. The goal is to obtain a range of RX path input level varying from -15 dB to 31 dB, while maintaining the noise contribution negligible. Figure 6. Signal Attenuator (ATT) and Low Noise Amplifier
Attenuation 2
RXP
Gain 5
Vref
LNA
RXN Attenuator MTC-20154
The input attenuator will have the following characteristics Table 9. Attenuator Characteristics
Data Input type Common mode voltage (forced) Maximum input differential voltage Input impedance Attenuation step Attenuation range Maximum attenuation error Digital interface Digital code - - 10 - 0 - - `11' -> 0 dB attenuation '00' -> -15 dB attenuation Min AC only, DC decoupled - VDD/2 VDD 14.47 5 - .05 2 - VDD+1Vd 19 - -15 - - V Vpdiff KOhms dB dB dB bits Typical Max Unity
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Table 10. LNA characteristics
Data Input common mode voltage Input differential voltage Maximum peak input differential voltage Output common mode voltage Maximum peak output differential voltage Amplification step Amplification range Input refered noise at max gain, min atten. (over a 36 kHz to 1.1 MHz band) Power consumption Digital interface Digital code - - '00000' -> 0 dB amplification 32 5 '11111' -> +31 dB amplification - - mW bits - - - - - 0.7 0 5.5 Min 1 1 AVDD/2 1 1 - 6.5 Typical AVDD/2 - - - - - 1.3 +31 8 Max V Vpdiff Vpdiff V Vpdiff dB dB nV/Hz Unity
RX Filters The combination of the external filter (an LC ladder filter typically) with the integrated lowpass filter provides: - echo reduction to improve dynamic range - DMT sidelobe and out of band (anti-aliasing) attenuation. - Anti alias filter (60 dB rejection @ image freq.) ATU-R-RX filters The integrated filter characteristics are shown in table 6. ATU-C-RX Filter This filter is the same as the one used for ATU-R_TX. Linearity of RX Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5 Vpd amplitude (total _1 Vpd) at the output of the RX-AGC amplifier (i.e: before the ADC) for the case of minimal AGC setting. Table 11. Integrated filter characteristics ATU-R-RX
Description Type Cut-off frequency Max. in-band ripple 4th order butterworth 1.104 MHz (f0) 0-2 dB Value/Units
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Table 12. Linearity of ATU-R-RX
f1 (0.5 Vpd) f2 (0.5 Vpd) S/IM3 (AGC = 0 dB) 300 kHz 200 kHz 59.5 dB @100 kHz 53.5 dB @400 kHz 43.5 dB @700 kHz 42.5 dB @800 kHz 500 kHz 400 kHz 59.5 dB @300 kHz 48.0 dB @600 kHz 700 kHz 600 kHz 48.0 dB @500 kHz 42.5 dB @800 kHz
Table 13. Linearity of ATU-C-RX
f1 (0,5 Vpd) f2 (0,5 Vpd) S/IM3 (AGC = 20 dB) 80 kHz 70 kHz 56.5 dB @60 kHz 56.5 dB @90 kHz
A/D Converter A pipeline architecture is used for the A/D converter. Table 14. A/D Converter specifications
Number of bits: Minimum resolution of the A/D converter Linearity error of the A/D converter (range: -6 dB FS) Full scale input range: Sampling rate: Maximum attenuation at 1.1 MHz: Latency: 13 bits 11 bits < 4 LSB (out of 13 bits) 1.1 Vpdif (+- 5 % @ 3.3 V) 8.832 MHz < 0.5 dB without in-band ripple 5 sampling clock periods
Power Supply Rejection The noise on the power supplies for the RX-path must be lower than the following: < 50 mVrms in-band white noise for any AVDD. Figure 7. Power Supply Rejection
dB -40 -50 -60 -70 Hz 1k 10k 100k 1M 10M
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TX Pre-driver Capability The pre-driver drives an external line power amplifier which transmits the required power to the line. Table 15. Pre-driver characteristics
TX drive level to the external line driver for max AGC setting External line driver input impedance: Pre-driver characteristics: gain range: common mode voltage: output common mode voltage: -9 dB...6 dB with step = 1 dB AVDB/2 30 nV/Hz resistive capacitive 2 Vpdif > 200 < 30 pF
TX Filter The TX filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A converter's output to suppress the image spectrum. For this reason they are realised in a time continuous approach. ATU-R-TX Filter The purpose of this filter is to remove out-of-band noise of the ATU-R-TX path echoed to the ATU-R-RX path. In order to meet the transmitter spectral response, additional filtering is (digitally) performed. The integrated filter has nominal characteristics shown in table 11: Table 16. ATU-R-TX filter characteristics
Description Input refered noise Max. input level Max. output level Type Cut-off frequency Max. in-band ripple 94 nV/ Hz 1 Vpd 1 Vpd 4th order chebychef 138 KHz (f0) 0.5 dB Value/Units
ATU-C-TX Filter Same filter as ATU-R-RX. Its purpose is now is to remove image frequency of the transmitted signal according the ANSI definition. Table 17. D/A Converter
Description Number of bits: Minimum resolution of the D/A converter Linearity error of the D/A converter Full scale output range: Sampling Rate: Latency: Value/Units 12 bits 11 bits < 1 LSB (out of 12 bits) 1 Vpdif +- 5% 8.832 MHz (or 4.416 in alternative mode) 1 sampling clock period
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Linearity of ATU-C-TX Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.25 Vpd amplitude (-6 dB FS) at the output of the pre-driver for the case of a total AGC = 0 dB. Table 18. Linearity of ATU-C-TX
f1 (0.25 Vpd) f2 (0.25 Vpd) S/IM3 (AGC = 0 dB) 300 kHz 200 kHz 59.5 dB @100 kHz 53.5 dB @400 kHz 43.5 dB @700 kHz 42.5 dB @800 kHz 500 kHz 400 kHz 59.5 dB @300 kHz 45.0 dB @600 kHz 700 kHz 600 kHz 48.0 dB @500 kHz 42.5 dB @800 kHz
Table 19. Linearity of ATU-R-TX
f1 (0.25 Vpd) f2 (0.25 Vpd) S/IM3 (AGC = 0 dB) 80 k 70 k 59.5 dB (60 k/90 k)
Power Supply Rejection The noise on the power supplies for the TX-path must be lower than the following: < 50 mVrms in band white noise for AVDD. < 15 mVrms in band white noise for Pre-driver AVDD. Voltage Controlled Crystal Oscillator A voltage controlled crystal oscillator driver is integrated in the MTC20154. Two nominal frequencies can be used: 35.328 MHz or 17.664 MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the VCXO control is depicted on the figure beside. Figure 8. Principle of the VCXO control (ATU-R)
AVDD VCOCAP IVCO AVDD Rref AVDD/22 -> AVDD/2
MTC-20154
500k +/- 30% 8 CTRLIN Ron=200 DAC VCXOUT
XTAL0
AGND
Freq. doubler MUX XTAL1 Clock
Ct -15V
R1
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The crystal's exact oscillation frequency can be tuned around the nominal frequency. This is needed in order to allow the system to minimize the clock phase shift between the LT and the NT modems. The information coming from the digital processor via the CTRLIN path is used to drive a 8 bits DAC (resistor ladder architecture) which generates a control current. This current is externally converted and filtered to generate the required control voltage for the varicap. The VCXO characteristics are given in the following table. Table 20. VCXO characteristics
Data Needed crystal accuracy Needed crystal frequency tuning range DAC resolution DAC output voltage range DAC differential non linearity error DAC integrated non linearity error VCXO nominal output current (Rref = 16.5 K AVDD = 3.3 V) Power consumption Min 50 100 - - - 95 - Typical - - 8 AVDD/2 - - 100 .225 Max - - - 1.5 4 105 - Unity ppm ppm bit V LSB LSB mA mW
PLL Based Frequency Doubler Dual crystal frequency can now be used needed when a 17.644 MHz crystal with the MTC20154 on-board crystal is used. A frequency doubler, build driver. However, a master clock up around a Phase Locked Loop (PLL), frequency of 35.328 MHz is still will then be used.
Digital Interface Control Interface The digital code setting for the MTC20154 configuration is sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched but they are overruled by the normal settings if the TEST pin is low. Control Interface Timing The control interface bits are considered valid on each positive edge of the master clock (CLKM). They will be sampled at this moment. The stop bit will trigger the internal data validation. The timing requirements are depicted in the following figure and table: Figure 9. Control Interface Timing diagram
CLKM CLKWD CTRLIN
Start bit
Th Ts
ctrl data bits
ctrl cmd bits 1 stop bit (high)
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Table 21. Receive / Transmit Protocol
Symbol Ts Th TDv Parameters Setup Time Hold time Data Valid min 7 ns 0.2 ns 0.5 ns typ - - - max - - 4 ns Remarks
Data set up and hold time are specified versus rising edge of CLKM Receive / Transmit Interface The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328 MHz data lines in the following table. If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. Table 22. Receive / Transmit Protocol
N0 RXD0 / TXD0 will contain RXD1 / TXD1 will contain RXD2 / TXD2 will contain RXD3 / TXD3 will contain b0 b1 b2 b3 N1 b4 b5 b6 b7 N2 b8 b9 b10 b11 N3 b12 b13 b14 b15
TX / TXE Signal Dynamic Range The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit representation coming from the digital processor. The maximal positive number is 214-1, the most negative number is -214, the 3 LSBs are ignored. Any signal exceeding these limits is clamped to the maximal value. Figure 10. TX/TXE Bit Map
sign
sign
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
n.u.
n.u.
n.u.
RX Signal Dynamic Range The dynamic range of the signal from the ADC is limited to 13 bits. Those bits are converted to a signed representation with a maximal positive number of 2 14-1 and a most negative number of 2 14. The 2 LSBs are filled with '0'. Figure 11. RX Bit Map
sign
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
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MTC20154
Receive / Transmit Interface Timing This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode). The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are transferred first. The MTC20154 generates a nibble clock (= master clock in normal mode, CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces. Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going edge of CLKM/CLKNIB. This holds for the data stream from MTC20154 and from the digital processor. Data, CLWD setup and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB. RXD is sampled with CLKM rising edge. Figure 12. TX/TXE/RX Digital Interface Timing
CLKM 35.328 MHz CLWD 8.832 MHz
TXDx/RXDx N0 CLKNIB 17.664 MHz CLWD 4.416 MHz N1 N2 N3
TXDx/RXDx N0 N1 OSR=2
Power Down The MTC20154 is placed in power-down mode when the PD pin is high. The system specifications are requiring different behavior of the MTC20154 under power down mode according to the fact that the MTC20154 is used at the LT or the NT side. The chip status is depicted in the following table: Table 23. Power Down
Power down LT side CLKM pin is replicating the XTALO input clock (no crystal used at LT side). System clock available CLKWD is generated. Digital blocks active Analog TX path is in powerdown External driver is forced to power UP Power down NT side Crystal driver + VCODAC are active CLKWD is generated. Digital blocks active, except for RX-I/O's - they are at low lovel Analog RX & TX are in powerdown External driver is forced to power DOWN
N2
N3
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MTC20154
Reset Function The MTC20154 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The system specifications are requiring different behavior of the MTC20154 under reset mode according to the fact that the MTC20154 is used at the LT or the NT side. The chip status is depicted in the following table: Table 24. Reset Function (N.B. The reset signal is dominant over the powerdown signal.)
Reset LT side CLKM pin is replicating the XTALO input clock (no crystal used at LT side). System clock available CLKWD is not generated. The pin stays at high level. Digital blocks are in reset: no activity Analog blocks are in powerdown External driver is forced to powerdown Reset NT side Crystal driver in power down: no CLKM signal available. No system clock avail-able. CLKWD is not generated. The pin stays at high level Digital blocks are in reset: no activity Analog blocks are in powerdown External driver is forced to powerdown
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MTC20154
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 12.20 10.20 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE AND MECHANICAL DATA
0.0066 0.0086 0.0086 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.480 0.401
0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031
TQFP64 (10 x 10 x 1.4mm)
D D1 A D3 A1 48 49 33 32
0.08mm ccc Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
0051434 E
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MTC20154
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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